---------- Forwarded message ----------
From:
Subrata Mukhopadhyay, ECC, IEEE Delhi Section <ieeedsec@giasdl01.vsnl.net.in> Date: Fri, Dec 4, 2009 at 4:46 PM
Subject: A series of seminars as part of the Workshop on Reliability and Physical Verification December 12, 2009 Block VI, Lecture Theatre I, IIT Delhi
To:
DELHI@listserv.ieee.org IEEE Circuits and Systems/Control Joint Chapter, Delhi, the IEEE Computational
Intelligence Society, Delhi Chapter, and FITT, IIT Delhi invite you to attend
A series of seminars as part of the
Workshop on Reliability and Physical Verification
December 12, 2009
Block VI, Lecture Theatre I, IIT Delhi
For registration, please e-mail
decworkshop@gmail.com confirm with Mr. Nalesh (99104 74163)
Dr. Kaushik Saha, ST Microelectronics: Design for Manufacturability
The talk will discuss the Motivation for DFM, Nature of Defects, Some
examples from Silicon Experience, Avoidance strategies, and an Overview of
Simulation, Analysis and DFY EDA Tools.
About the Speaker: Dr. Kaushik Saha joined STMicroelectronics Ltd.(previously
SGS-Thomson Microelectronics Ltd) in 1996, after having done his B.Tech,
M.Tech. and Ph.D. from Indian Institute of Technology, Delhi. He joined the
organization as a designer of semiconductor memories in the Memory Products
Group. Subsequently, he worked for the Applications Lab of the company and
was involved in the design of consumer electronics systems around the
devices designed and fabricated by the company. He is currently Design Unit
Manager of the India unit of the Advanced Systems Technologies group of
STMicroelectronics, which is the group involved in research and development
of future generations of devices and systems planned by the company for the
markets of tomorrow. He also holds an Adjunct Faculty position in IIT-Delhi
where he teaches advanced topics in VLSI design.
Dr. Mysore Sriram, Intel: Analysis and optimization of VLSI power grids
The analysis and optimization of on-die VLSI power grids is becoming
increasingly significant, as power supply voltages trend steadily lower, wire
geometries shrink and current densities stay flat. There are three kinds of
effects in power grids that may impact the reliability and performance of a
chip. Self-heating could cause power grid wires to melt, causing the chip to
fail. Electromigration, a process by which metal atoms migrate over time in the
direction of electron movement, could cause shorts between adjacent wires
and reduce mean time to failure. IR drop effects could reduce the effective
power supply voltage and cause circuits to malfunction or run slower.
Analyzing power grids to predict these effects is a complex problem due to the
extremely large number of layout objects in a typical VLSI power grid. For
example, the full-chip power grid for a server CPU design could have over two
billion nodes. This talk will describe these challenges and some of the solution
techniques that are in use today. We will also discuss the need for automation
in solving power grid issues and optimizing grid design.
About the Speaker: Mysore Sriram is a Principal Engineer with the Design and
Technology Solutions group in Intel Technology India, Bangalore. He has a B.
Tech in Electronics and Communication from the Indian Institute of
Technology, Madras, and a MS and Ph.D. in Electrical and Computer
Engineering from the University of Illinois at Urbana-Champaign. Sriram joined
Intel in Santa Clara in 1993, and has worked on developing several generations
of physical design CAD tools. Over the past few years, he has worked on
floorplanning and layout of Intel's multi-core server CPU designs. Sriram's
technical interests lie in the areas of placement and routing, optimization
algorithms and VLSI interconnect analysis and optimization. Outside of work,
Sriram enjoys drawing portraits, hiking and music.
Biswadeep Chatterjee, Intel: Crosstalk Analysis and Optimization in pre-silicon
design
As VLSI technology scaling continues, designers have to deal with problems of
signal integrity. Capacitive cross-coupling between adjacent wires can lead to
glitches and/or delay variations. A detailed analysis of such cross-couple
effects is necessary during static timing analysis to accurately estimate
effects of proximal nets on the electrical behavior of a given net and fix any
functional/timing failures arising out of such effects. Also, precautions are
necessary during pre-silicon design to ensure that signal integrity problems do
not lead to failures during circuit operation. Over the past decade, EDA tools
and design flows have evolved to deal with signal integrity problems. This
session will deal with various aspects of signal integrity and provide an
overview of how a design methodology needs to be architected to trap and
eliminate such problems at the earliest possible design stage.
About the Speaker: Biswadeep Chatterjee has 13+ years of industry
experience in the domain of VLSI Design Automation and CAD tools
development for System-on-chip products catering to wireless, communication
and chipset business. He has led and managed design automation teams in
Intel which were responsible for providing design methodology and
infrastructure planning support to silicon design teams. Biswadeep currently
works as an enterprise architect in Intel's Platform and Design Capability
Enhancement organization and owns the charter to evangelize innovative
IT/computing solutions to improve silicon design productivity. Biswadeep
started his career with Texas Instrument's ASIC Product Develop Center in
Bangalore and held multiple engineering positions to develop in house
automation solutions in the domains of place and route, cell layout, library
characterization and modeling and design kit delivery. Biswadeep is involved in
Intel India's Higher Education program as a mentor responsible for providing
technical direction and projects for different Indian universities and institutes
of technical education. For a while, Biswadeep was entrusted with the
responsibility of managing Intel India research ecosystem and research
engagements with academia and government agencies. His interests include
physical design algorithms, reliability verification methodologies and also
providing training/mentoring in domains of cross-site and stakeholder
management.
Biswadeep completed his graduation from Department of Electronics and
Telecommunications in Jadavpur University, Kolkata and later followed it up
with MS in Software Systems from BITS, Pilani.
Theertham Srinivas, National Semiconductors: Reducing the Design Time of
Amplifiers
The aim of the presentation is to reduce the design time required to design
amplifiers used in switched capacitor circuits. Apart from stability issue, there
are two main issues that consume time while designing an amplifier. First is the
calculation of amplifier parameters like Open-loop gain, Gain bandwidth product
and slew rate. Second is the optimization of the transconductances of the
MOSFETs in the circuit. This paper consists of three sections:
About the Speaker: Theertham Srinivas obtained his B.Tech in Electronics and
Communications in 1999 from NBKR Institute of Science & technology, and his
M.Tech in Microelectronics from IIT Madras in 2001. He was a Design Engineer
at Sanyo LSI Technologies from 2001 to 2005, and has been with National
Semiconductor India Pvt Ltd since then, earlier as a Senior Design Engineer
and presently as a Staff Engineer. His current role involves defining the
architecture and designing Analog and Mixed Signal Circuits for high precision
Data Converters.
Dr. Anurag Seth, Kawasaki Microelectronics: EM issues in SoC design
The presentation would cover an introduction to EM issues in SoC design at
advanced nodes, EDA solutions to address the same, and the overall impact on
design flow(s).
About the Speaker: Anurag Seth is currently heads Kawasaki Microelectronics
(K-Micro's) India branch as its Managing Director - the team consists of an
Analog IP team and a ASIC CAD flow methodology team working out of the
Bangalore office besides being responsible for business development for K-
Micro in India. He holds a Masters Degree in Computer Science from BITS Pilani
and an Executive Masters in International Business from IIFT, New Delhi.
Anurag has about 20 years of experience working in SoC designs, EDA Tool
Development, CAD flows/methodoliges as well as system level design. Prior to
K-Micro, Anurag spent 8 years heading the Digital IC Implementation team's
India R&D which was responsible to delivering key components of Cadence's
Encounter Digital Design Platform, more specifically, Timing Analysis (including
SSTA), IR Drop Analysis, Crosstalk analysis, physical optimization and mixed
signal flows. Before Cadence, Anurag was at Motorola Semiconductor Product
Sector (now, Freescale) and managed a design as well as internal CAD team
working on wireless baseband processsor design.
